1. Field of the Invention
The present invention relates to a level transition determination circuit and a method for using the same.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
With the rapid development of broadband applications, such as, high definition video programs, online learning, video conferencing and chatting, and cloud computing, users have ever increasing requirements on the bandwidth. Optical networks have become a mainstream technique in the broadband application due to a stable transmission quality with high bandwidth and high speed. Currently, a Passive Optical Network (PON) technique is mostly applied in the industry, in which an Optical Distribution Network (ODN) is used to split an optical signal into multiple paths (most commonly, 16 paths or 32 paths) to be sent to clients, thereby reducing the use of fibers.
The PON has a Point to Multi-Point (PMP) topology architecture, and uploaded data may be converged at the same fiber by the ODN. Therefore, the uploaded data should be transferred in a Time Division Multiplexing (TDM) manner according to a communication protocol, such as IEEE 802.3ah standard or ITU G.983/G.984 standard. The TDM technique refers to dividing a signal channel with time, so as to divide the signal channel into a plurality of time slots, only one user can transfer or receive data in each time slot, and therefore, the time for each user to transfer the data is greatly reduced. In this case, if a conventional data recovery circuit is used to perform recovery, time spent for locking and recovery is too long, which results in waste of bandwidth utilization efficiency. Therefore, for the burst data transmission action, an optical network terminal (ONT) must be provided with a burst-mode receiver to rapidly recover the clock and phase of received data, so as to utilize the bandwidth more effectively.
FIG. 1 is a schematic block diagram of a conventional data recovery circuit based on a phase locked loop (PLL). The data recovery circuit 10 includes a phase/frequency detector 12, a loop filter 14, and a voltage controlled oscillator (VCO) 16. The phase/frequency detector is used for comparing a phase of input data Data_in and a phase of output data Clk_out generated by the VCO 16 to determine whether a phase difference exists therebetween. When the phase difference exists (Δθ≠0), the phase/frequency detector 12 outputs a phase difference signal PD. The loop filter 14 receives the phase difference signal PD to adjust a level of an output signal Vcont, so as to change the frequency of the VCO 16, until the phase is calibrated. At this point, the data recovery circuit 10 reaches a locked stable state.
If it is intended to design a data recovery circuit having rapid locking characteristic, adopting an oversampling technique may be a feasible method. The oversampling technique is adopted to perform oversampling on received serial input data, so as to obtain edge information of data bits. FIG. 2 is a schematic view of a conventional three-times oversampling technique. When performing the three-times oversampling, a clock frequency of three times a bit data rate is used to perform sampling on bit data in the serial input data. Then, by using sampled data states, an Exclusive-OR (XOR) operation is performed on two adjacent states, and bit edge information of the serial input data is obtained through computation with a group of digital circuits.
After obtaining the bit edge information, a sampling result that is farthest away from the data edge is selected from the three sampling results to serve as the valid data bit. By using the above method, the valid data bit may be obtained after computing several groups of bit edge information, in which a feedback mechanism needs not to be included, and thus the method is applicable to applications requiring rapid locking.
However, in high-frequency circuit application, if it intends to generate sampling clock of high multiple oversampling, the difficulty thereof is increased as well, and therefore, a concept of processing serial input data by a plurality of groups of digital circuits in parallel is introduced, which is a solution for the frequency bottleneck. Therefore, an improved level transition determination circuit for serial input data and a method for using the same are provided, so as to determine level transition points of the serial input data correctly, thereby obtaining a valid data bit.